The present invention relates, in general, to the field of integrated circuit (IC) devices. More particularly, the present invention relates to a high-speed, low-power input buffer for integrated circuit devices including memories such as dynamic random access memory (DRAM), synchronous DRAM, synchronous static random access memory (SRAM).
Signaling between integrated circuits is typically done using one of several signaling protocols. Most of these protocols specify a reference voltage (VREF). The input (VIN) is a valid logic level “high” when it is above the level of VREF by a specified voltage (Vih) and the input is a valid logic level “low” when it is below the level of VREF by a specified voltage (Vil). The Stub Series-Terminated Logic (SSTL) interface standard intended for high-speed memory interface applications is an example of just such a protocol and it would be highly advantageous to provide an input buffer which simultaneously exhibits higher speed operation while requiring reduced power levels as compared to conventional circuit implementations.